The present invention relates to integrated circuit devices, and in particular high voltage semiconductor switching devices such as high voltage transistors, power MOSFETs, power IGBTs, thyristors, MCTs, and the like (hereinafter called power devices).
Conventional power devices are fabricated by conventional semiconductor processing techniques on a single crystalline semiconductor substrate such as a silicon wafer. Conventional semiconductor processing techniques include doping and implanting, lithography, diffusion, chemical vapor deposition (CVD), wet and dry etching, sputtering, epitaxy, oxidizing, among others. A complex sequence of these processing techniques is often required to produce is a high voltage device having a breakdown voltage within the 30 to 1200 volt range.
A limitation with the conventional power device is its shallow junction region. The shallow junction region often creates low junction curvature and reduces the breakdown voltage of the device. This lower breakdown voltage is often an undesirable result for high voltage applications.
Industry has proposed or even attempted to overcome such limitation with use of a guard ring formed adjacent to the main junction of the power device. The guard ring typically provides a junction termination technique for the convention power device. A conventional guard ring is often formed by selectively placing certain dopants around the periphery of the main junction, typically in a xe2x80x9crace trackxe2x80x9d or xe2x80x9cringxe2x80x9d type pattern. The dopants often include impurities of the same impurity type as the main junction. Ideally, the guard ring keeps the main junction in its place.
However, as industry demands for power devices with even higher breakdown voltages and even smaller device features, the presence of contamination on certain portions of a convention guard ring structure detrimentally effects an electric field therein, thereby degrading the breakdown voltage of the device. Accordingly, the presence of contamination often creates a resulting power device that is unstable, unreliable, or the like.
Another technique often used to preserve the breakdown voltage of the device is to form a field plate located between certain guard rings for the purpose of reducing electric fields thereby. The field plate is formed overlying an oxide layer, also located overlying regions between the guard rings. Ideally, lower electric fields at such location should tend to increase the breakdown voltage of the device. However, a limitation with the field plate structure often occurs with power devices having higher breakdown voltages.
For example, power devices with even higher breakdown voltages produce an even higher electric field underneath portions of the oxide layer. The higher electric field generally promotes certain hot electron effects such as electrons being injected and trapped into portions of the oxide layer, and the like. As charge builds up in the oxide layer from the trapped electrons, the conventional device often experiences detrimental effects such as current leakage, voltage instability, unreliability, and the like.
From the above, it is seen that a method and structure for providing a device with a high breakdown voltage that is easy to manufacture, reliable, and cost effective is often desired.
The present invention provides an power integrated circuit device with a combination of multiple guard rings and field plates for the purpose of achieving high voltage applications. Benefits of the present invention are achieved in the context of known technology.
The present invention provides a power device that includes a semiconductor substrate having a top surface with an active region, a guard ring region, and a peripheral region. The active region includes a junction region. The present power device also includes a plurality of guard rings formed onto the semiconductor substrate in the guard ring region, typically located between the active region and the peripheral region. The plurality of guard rings has a first guard ring nearest to the junction region and a last guard ring nearest to the peripheral region. The present power device further has a dielectric layer overlying the top surface and having portions between each of the plurality of guard rings. The dielectric layer also includes a portion between the junction region and the first guard ring, and another portion between the last guard ring and the peripheral region. A field plate layer is also provided. The field plate layer is overlying each of the dielectric layer portions between each of the plurality of guard rings. The field plate layer is also overlying the dielectric layer portion between the junction region and the first guard ring. The field plate layer further overlies the dielectric layer portion between the last guard ring and the peripheral region.
In an alternative embodiment, the present invention provides a power device with a semiconductor substrate that includes a top surface with an active region, a guard ring region, and a peripheral region. The active region includes a junction region. The present power device also includes a plurality of guard rings formed onto the semiconductor substrate in the guard ring region. The guard ring region is located between the active region and the peripheral region. The plurality of guard rings includes at least a first guard ring nearest to the junction region and a last guard ring nearest to the peripheral region. A dielectric layer overlying the top surface and having portions between each of the plurality of guard rings is also provided. The dielectric layer also has a portion between the junction region and the first guard ring. A dielectric layer portion between the last guard ring and the peripheral region is further provided. The present power device includes a field plate layer. The field plate layer has a plurality of field plates overlying each of the dielectric layer portions between each of the plurality of guard rings, and a field plate located between the junction region and the first guard ring. The field plate layer also includes a plurality of field plates overlying the dielectric layer portion between the last guard ring and the peripheral region.
In a further alternative embodiment, the present invention provides a method of forming a guard ring structure. The present method includes providing a partially completed semiconductor device with an active region, guard ring region, and peripheral region. The active region includes a junction region, and the guard ring region exists between the active region and the peripheral region. The guard ring region also has a plurality of diffusion region. The present method also includes steps of forming a dielectric layer overlying the partially completed semiconductor substrate, and forming a field plate layer overlying the dielectric layer. A step of defining the dielectric layer and field plate layer to form a plurality of openings over the diffusion regions is also provided. The dielectric layer and field plate layer is also defined to expose the junction region and the peripheral region. The present method further has a step of providing implants into the openings to define a plurality of guard rings. The plurality of guard rings includes at least a first guard ring proximate to the junction region and a last guard ring proximate to the peripheral region.
A further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.